Publications
Export 18 results:
"Energy minimization at all layers of the data center: The ParaDIME Project",
19th Conference on Design, Automation, and Test in Europe (DATE 2016), 03/2016.
"Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm",
24th International Conference on Parallel, Distributed and Network-Based Processing (PDP 2016), 02/2016.
"Trigeneous Platforms for Energy Efficient Computing of HPC Applications",
22nd annual IEEE International Conference on High Performance Computing (HiPC 2015), Bengaluru, India, IEEE, 12/2015.
"VPM: Virtual Power Meter Tool for Low-Power Many-Core/Heterogeneous Data Center Prototypes",
33rd IEEE International Conference on Computer Design (ICCD 2015), New York, USA, IEEE, 10/2015.
"FAcET: Fast and Accurate Power/Energy Estimation Tool for CPU-GPU Platforms at Architectural-Level (Nominated for the BEST PAPER AWARD)",
28th IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (IEEE-SoCC 2015), Beijing, China, IEEE, 09/2015.
"ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers",
Microprocessors and Microsystems, 06/2015.
Download: 1-s2.0-s0141933115000848-main.pdf (3.94 MB)
"Heterogeneous Platform to Accelerate Compute Intensive Applications",
The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, British Columbia, Canada, IEEE, 05/2015.
"An Energy Efficient Hybrid FPGA-GPU based Embedded Platform to Accelerate Face Recognition Application",
COOL Chips XVIII, Yokohama, Japan, IEEE Micro, 04/2015.
"System-Level Power & Energy Estimation Methodology and Optimization Techniques for CPU-GPU based Mobile Platforms",
In the proceedings of 12th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESWEEK 2014), New Delhi, India, IEEE, 10/2014.
"VPPET: Virtual Platform Power and Energy Estimation Tool for Heterogeneous MPSoC based FPGA Platforms",
In the proceedings of 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014), Palma de Mallorca, Spain, IEEE, 10/2014.
"DESSERT: DESign Space ExploRation Tool based on Power and Energy at System-Level",
In Proceedings of 27th IEEE International System-on-Chip Conference (SoCC 2014), Las Vegas, USA, 09/2014.
"ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy",
In Proceedings of 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2014), Verona, IEEE/Euromicro, 08/2014.
"ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy at the Architectural Level",
ICT Energy Newsletters, Barcelona, 07/2014.
"System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platform",
In Proceedings of IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2014), Tampa, Florida, IEEE, 07/2014.
"PETS: Power and Energy Estimation Tool at System-Level",
The International Symposium on Quality Electronic Design (ISQED 2014), Santa Clara, California, USA, IEEE, 03/2014.
"Power Estimation Tool for System on Programmable Chip based Platforms",
22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2014), Monterey, California, USA, ACM, 02/2014.
"ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy",
Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and Transactional Memory Systems (DMTM), In conjunction with Hipeac 2014, Vienna, Austria, 01/2014.
"System-Level Power Estimation Tool for Embedded Processor based Platforms",
6th Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO14), In conjunction with Hipeac 2014 Conference, Vienna, Austria, ACM, 01/2014.
