Parallel Distributed Infrastructure for Minimization of Energy

Santhosh's blog

ParaDIME @ HiPEAC CSW, 2015

Wed, 2015-09-23

ParaDIME was invited to present its results related to Power and Energy estimation at the System-Level at the TACLe Thematic Session. Link to the talk: https://www.hipeac.net/events/activities/7288/tacle/#fndtn-program. This talk was well attended by 55 people from 34 different institutions.

 

Abstract of the talk:

This talk was about the work done in the ParaDIME FP7 project about how to design and implement energy-aware computing and power estimation at the system-level for various types of low-power processors prototypes and to help improving energy efficiency of future computing systems. Power and energy consumption of processors are steadily increasing and the work performed by them at the data centers is not proportional to the power dissipated, where every µA is a revenue for the entity. On the one hand, the hardware community is proposing various methodologies to address this issue such as low-power processors, heterogeneity, etc. to reduce the power of the servers. On the other hand, the system software community proposes mechanisms such as virtual machines (VMs), work-load scheduling, etc. to increase the utilization of the processor. To properly evaluate the impact of these mechanisms, we need a fast and accurate power estimation tool at the system-level.

 

The link of the video will updated soon. 

ParaDIME @ ARM Research, Cambridge

Mon, 2015-09-21

ParaDIME disseminated its research results as a part of the invited talk series at the ARM Research in Cambridge on 18th of September.  This talk was attended by people from both ARM Cambridge and and from ARM, Austin, USA through a live feed.

First part of the talk was focused on how to design and implement energy-aware computing and power estimation in servers, MPSoCs and various types of data centers to help achieve an energy efficient computing future. Power and energy consumption of data centers are steadily increasing and the work performed by the data centers is not proportional to the power dissipated, where every µA is a revenue for the entity. On the one hand, the hardware community is proposing various methodologies to address this issue such as low-power processors, heterogeneity, etc. to reduce the power of the servers. On the other hand, the software community proposes mechanisms such as virtual machines (VMs), work-load scheduling, etc. to increase the utilization of the processor. In order to properly evaluate the impact of these mechanisms, we need an accurate power monitoring and estimation tool at the hardware host level, the VM level and the system-level. Achieving the target exascale performance and designing a green cloud computing infrastructure require the design of dynamic and smart techniques that recognize the hardware-software characteristics and optimization of the trade-off among performance, energy, and power in an application-aware manner. Second part of the talk was focused on a novel heterogeneous platform with the integration of three devices (CPU, GPU, FPGA) into a single system, i.e. Trigeneous platforms, to efficiently accelerate and to minimize energy of computation intensive applications in both high-performance computing and embedded system domains.

ParaDIME’s research paper has been nominated for Best Paper Award at IEEE-SoCC 2015 Conference

Tue, 2015-09-22

The paper entitled as FAcET: Fast and Accurate Power/Energy Estimation Tool for CPU-GPU Platforms at Architectural Level authored by Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman Unsal and Adrian Cristal has been nominated the Best Paper Award at IEEE-SoCC 2015. This paper proposes a powerful power estimation tool at the system-level and a necessary tool for both application and architecture designers.

 

Abstract the paper:

This paper proposes a novel fast and accurate architectural-level tool to estimate power and energy (FAcET) for heterogeneous (CPU-GPU) system architecture based platforms. FAcET consists of two components. The first is a set of generic parametrizable power models generated by characterizing the functional-level activities for different blocks of the chosen platforms. The second is a simulation-based architectural-level prototype that uses SystemC (JIT) simulators to accurately evaluate the parameters of the corresponding power models of the first component. The combination of the two components leads to a novel power and energy estimation methodology at the architectural level that provides a better balance between speed and accuracy. The efficacy of the FAcET tool is verified against measurements taken on real board platforms, which consist of low-power ARM quad-core processors (Cortex-A7, -A9 and -A15), NVIDIA GPUs (Quadro 1000M, Quadro FX5600, Tegra K1, and GTX480) and heterogeneous platforms (NVIDIA Tegra3 and NVIDIA Jetson TK1). Power and energy estimation results obtained with FAcET deviate in less than 3.6% for quad-core processors, 6.5% for GPU, 10% for heterogeneous multiprocessor based systems from the measurements and estimation is 15x faster than state-of-the-art tools.

 

About the conference:

In its 27 years of history, the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for sharing advances in system-on-chip (SoC) technologies, designs, tools, test, verification and applications. Held at changing locations in the USA, Europe and Asia, SOCC is attracting researchers and engineers from all over the world to exchange knowledge, share experiences and establish collaborations with colleagues. Each year, the IEEE-SoCC Programme Committee selects 3 papers to be nominated for the best paper award across 300˖ papers.

Call For Paper: The 2nd ICT-Energy International Doctoral Symposium (ICT-EIDS)

Tue, 2015-03-31

The 2nd ICT-Energy International Doctoral Symposium

                                            September 16, Bristol, UK                                                 

 

Call for Paper:

The doctoral symposium is a part of ICT-Energy workshop (2015). This symposium is a great opportunity for PhD students to present their thesis work to a broad audience in the ICT community from both industry and academia. The forum may also help students to establish contacts for entering into research related to minimization of energy from various layers. In addition, representatives from industry and academia get a glance of state-of-the-art in the energy minimization field.  Topics of interest include, but are not limited to:

- Power- and thermal-aware algorithms, software and hardware

- Low-power electronics and systems

- Power-efficient multi/many-core chip design

- Sensing and monitoring

- Power and thermal behavior and control

- Data centers optimization

- Smart grid and microgrids

- Power-efficient delivery and cooling

- Reliability, life-cycle analysis of IT equipment

- Renewable energy models and prediction

- Matching energy supply and demand

- Smart transportation and electric vehicles

- Smart buildings and urban computing

- Energy harvesting, storage, and recycling

 

Eligibility

The following two classes of students are eligible: students who are close to finishing or second year in their Ph.D thesis work and post-doctoral candidates.

 

Benefits

  • A presentation (25 mins) at the Doctoral Forum
  • Contacts to professionals from industry and academia
  • Possibility to publish the extended abstract in the ICT-Energy newsletters and website

Submission

Submissions need to contain

  • The full contact address, with affiliation, phone, e-mail
  • A 2-pages extended abstract describing the novelties and advantages of the thesis work of not more than 2400 words (PDF). The abstract should also include name and affiliation. Figures may be included as far as the 2-page limit is not exceeded.
  •  ICT-Energy Newsletters formatting instruction and template can be downloaded from the link given in this page below.

Important dates

 

- Submission deadline: July 24th, 2015 (by email) (EXTENDED)

- Notification of acceptance: Aug 3th, 2015 (by email)

- Presentation at PhD Forum: September 16th, 2015

 

Submit this material to the emails given below:

 Contacts

Dr. Adrian Cristal

Nexus I - Planta 3

C/ GRAN CAPITA, 2-4

BARCELONA

08034

Email: adrian.cristal@bsc.es

 

Dr. Santhosh Kumar Rethinagiri

Nexus I - Planta 3

C/ GRAN CAPITA, 2-4

BARCELONA

08034

E-mail: santhosh.rethinagiri@bsc.es

 

 

Call for Posters:

You are also invited to submit proposals for poster sessions by e-mail, to Santhosh Kumar Rethinagiri, Poster Chair: santhosh.rethinagiri@bsc.es

Extended abstract submissions should be ONE page, formatted using the paper proceeding template given in the webpage. They are refereed primarily based on their relevance to the conference. Accepted abstracts will be published in the Proceedings of the ICT-Energy newsletters. All participants in this track will have an opportunity to present a poster and a short talk. Submission of a paper to the track signifies an agreement to have one author present the work at the conference. 

 

Author Schedule (Poster):

 

  • AUG 15th - Poster Abstract Submission (by e-mail)
  • AUG 20th - Poster Abstract Submission (by e-mail)

 

Chairs

Adrian Cristal (Barcelona Supercomputing Center)

 

Poster Chair
Santhosh Kumar Rethinagiri (Barcelona Supercomputing Center)
 

Committee Members

Osman Unsal (Barcelona Supercomputing Center)

Kerstin Eder (University of Bristol)

Oscar Palomar (Barcelona Supercomputing Center)

John Gallagher (Roskilde University)

Javier Arias (Barcelona Supercomputing Center)

Luca Gammaitoni (NIPS - University of Perugia)

Hossein Mamaghanian (EPFL)

Douglas J Paul (University of Glasgow)

Giorgos Fagas (Tyndall National Institute - University College Cork)

Micro-Energy day

Thu, 2014-06-26

On June 26th Barcelona Supercomputing Center and ParaDIME will celebrate the fourth Micro-Energy Day as part of the activities in the ICT-Energy Coordination Action! The initiative is presented in www.microenergyday.eu and is part of the initiatives organized during the 2014 European Sustainable Energy Week.  Join us in Perugia and Barcelona to celebrate the importance of the micro-energy in our daily life.
 
Micro-energy refers to the energy that is often disregarded as unimportant but actually plays a significant role in our daily life. As an example… when you run out of battery in your mobile phone and really need to make that call!!! The amount of energy involved in this case is really very small compared to the energy required to drive a car, but you definitely notice when it's not there…
 
In Barcelona: Join us in the Torre Girona Chapel to learn about micro-energy or just download our flyer!

Micro-Energy Day Flyer page 1Micro-Energy Day Flyer page 2Micro-Energy Day flyer on BSC premisesGroup discussing Micro-Energy Day with flyersTwo people discussing Micro-Energy Day with flyersVisitors to MareNostrum on Micro-Energy Day

ParaDIME in ICT Energy Workshop

Tue, 2014-04-01

ICT-Energy Community Workshop - Barcelona, 23-25 April 2014

 

ICT-Energy is a consortium among research groups interested in the role of energy in ICT devices.

The workshop will allow extended discussions and therefore foster cooperation between the project partners and the groups participating to the consortia.

The first day of the meeting is devoted to a short training course with 4 lectures on basic, introductory aspects of the science of ICT-Energy. The workshop is open to the participation of all the interested people. For the complete agenda, please visit the website. Please confirm your participation to emma.torrella [@] bsc.es .

 

ParaDIME in FPGA 2014

Wed, 2014-02-26

ParaDIME member Santhosh Kumar Rethinagiri presented his work at The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for presentation of advances in all areas related to FPGA technology.

ParaDIME at ISQED 2014

Tue, 2014-03-04

ParaDIME members Santhosh and Halil presented their work done in the project at The 16th International Symposium on Quality Electronic Design (ISQED 2014)—the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.

ParaDIME in RAPIDO 2014

Wed, 2014-01-22
ParaDIME member Santhosh Kumar Rethinagiri presented his work at Rapid Simulation and Performance Evaluation (RAPIDO) workshop in Vienna, Austria. 
 

ParaDIME in DMTM Workshop

Wed, 2014-01-22

ParaDIME members Oscar and Yarco presented their work done in the project at the Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and Transactional Memory Systems (DMTM) at Vienna, Austria.

Palomar, O.G. YalcinS K. RethinagiriO. UnsalA C. Kestelman, And G. Alioto"ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy",

Hayduk, Y.A. Sobe, And P. Felber"Dynamic parallel message processing with transactional memory in the actor model", 

ParaDIME in HiPEAC Conference

Tue, 2014-01-21
http://www.paradime-project.eu/system/files/news/images/img_08501.jpg

ParaDIME members Oscar and Santhosh from BSC presented the ParaDIME project at HiPEAC 2014 conference in Vienna, Austria. 

ParaDIME in HiPEAC newsletter

Wed, 2014-01-01

A presentation of the ParaDIME project appeared in the January 2014 quarterly edition of the HiPEAC info newsletterHiPEAC is the European Network of Excellence on High Performance and Embedded Architecture and Compilation.

CALL FOR PAPERS: ICT-Energy PhD Forum

Wed, 2014-04-02

ICT-Energy PhD Forum 2014, Barcelona (Spain)         

23-25 April 2014                  

Call for Submissions

The PhD forum is a part of ICT-Energy workshop (2014). This forum is a great opportunity for PhD students to present their thesis work to a broad audience in the community from “Toward Zero-Power ICT” (ZEROPOWER) and the novel “MINECC” (Minimising energy consumption of computing to the limit) both industry and academia. The forum may also help students to establish contacts for entering into research related minimization of energy from various layers. In addition, representatives from industry and academia get a glance of state-of-the-art in this energy minimization field.

 

Eligibility

The following two classes of students are eligible:

  • Students who are close to finishing or 2nd year in their thesis work.
  • Students within partner institutions of ICT-Energy consortium and MINECC projects associated in ICT-Energy consortium.

Benefits

  • A presentation (25 mins) at the PhD Forum
  • Contacts to professionals from industry and academia
  • Possibility to publish the extended abstract in the ICT-Energy newsletters and website

Submission

Submissions need to contain

  • The full contact address, with affiliation, phone, e-mail
  • A 2-page extended abstract describing the novelties and advantages of the thesis work of not more than 1600 words (PDF). The abstract should also include name and affiliation. Figures may be included as far as the 2-page limit is not exceeded.
  •  ICT-Energy Newsletters formatting instruction and template can be downloaded from the attachments given in this page below.

Important dates

- Submission deadline: April 7th, 2013

- Notification of acceptance: April 10th, 2013

- Presentation at PhD Forum: April 24th, 2014

Submit this material to the emails given below:

 

Contacts

Dr. Adrian Cristal

Nexus I - Planta 3

C/ GRAN CAPITA, 2-4

BARCELONA

08034

E-mail: adrian.cristal@bsc.es

 

Dr. Santhosh Kumar Rethinagiri

Nexus I - Planta 3

C/ GRAN CAPITA, 2-4

BARCELONA

08034

E-mail: santhosh.rethinagiri@bsc.es

 

Pilar Callau

Nexus I - Planta 3

C/ GRAN CAPITA, 2-4

BARCELONA

08034

E-mail: pilar.callau@bsc.es